What is MDC and MDIO?
What is MDC and MDIO?
Electrical specification The MDIO interface is implemented by two signals: MDIO Interface Clock (MDC): clock driven by the MAC device to the PHY. MDIO data: bidirectional, the PHY drives it to provide register data at the end of a read operation.
What is MDIO used for?
Management Data Input/Output, or MDIO, is a 2-wire serial bus that is used to manage PHYs or physical layer devices in media access controllers (MACs) in Gigabit Ethernet equipment.
What is RGMII in Ethernet?
The RGMII interface is a dual data rate (DDR) interface that consists of a transmit path, from FPGA to PHY, and a receive path, from PHY to FPGA. Both paths have an independent clock, 4 data signals and a control signal. The RGMII standard specifies that data and clock be output simultaneously (ie.
Is Mdio same as I2C?
MDIO – A short history For most pluggable optical transceivers the interface used for monitor and control is the I2C interface. Defined as part of MII in IEEE802. 3 clause45, MDIO can also be used in high speed optical transceivers like CFP, CFP2 or CFP4 instead of 100 Megabit.
What is Sgmii?
The serial gigabit media-independent interface (SGMII) is the interface with the lowest pin count available for connecting compatible MACs and PHYs. It consists of pairs of Txdata, Rxdata, and Rx Ref Clk data pins.
What does RGMII mean?
The reduced gigabit media-independent interface (RGMII) uses half the number of data pins as are used in the GMII interface. This reduction is achieved by running half as many data lines at double speed, time multiplexing signals and by eliminating non-essential carrier-sense and collision-indication signals.
Is Mdio open drain?
mdio – Inout * A bidirectional pin that transmits or receives data. The pin connected to mdio should be configured as Open Drain Low and the Input Sync Mode should be configured as Double-Sync.
What is the use of MDIO interface in a PHY?
A PHY management interface, MDIO, used to read and write the control and status registers of the PHY in order to configure each PHY before operation, and to monitor link status during operation. The MDIO interface is implemented by two signals: MDIO Interface Clock (MDC): clock driven by the MAC device to the PHY.
What are the pull-up resistor requirements for the MDIO?
The MDIO requires a specific pull-up resistor of 1.5 kΩ to 10 kΩ, taking into account the total worst-case leakage current of 32 PHYs and one MAC. Before a register access, PHY devices generally require a preamble of 32 ones to be sent by the MAC on the MDIO line. The access consists of 16 control bits, followed by 16 data bits.
How many opcodes are there in the MDIO header?
The first field in the MDIO header is the Preamble. During the preamble, the MAC sends 32 bits, all ‘1’, on the MDIO line. The Start field consists of 2 bits and always contains the combination ’01’. The Opcode consists of 2 bits. There are two possible opcodes, read ’10’ or write ’01’.
What is the maximum clock rate for MDC?
The MDC can be periodic, with a minimum period of 400 ns, which corresponds to a maximum frequency of 2.5 MHz. Newer chips, however, allow faster accesses. For example, the DP83640 supports a 25 MHz maximum clock rate for MDC.